With an increase in density of a large scale integrated circuit (hereinafter, referred to as an LSI), a circuit pattern has been miniaturized.
In order to integrate a large number of semiconductor devices into a small area, the semiconductor devices must be formed to be small in size. To this end, a width and a space of a pattern to be formed should be made small.
With the current trend for miniaturization, oxide embedded in a fine structure, particularly, in a narrow void structure (groove) which is deep in a vertical direction and narrow in a width direction has reached its technical limits when the embedding of the oxide is performed by a CVD method. In addition, with the miniaturization of transistors, a thin and uniform gate insulating film or gate electrode is required to be formed. Further, it is required to reduce a processing time for one substrate in order to improve productivity of semiconductor devices.
Since a minimal processing size of a semiconductor device required by a latest LSI, DRAM (Dynamic Random Access Memory), or flash memory is being less than 30 nm in width, the miniaturization, improved manufacturing throughput, or low processing temperature becomes difficult while maintaining the quality. For example, when a gate insulating film or a gate electrode is formed, a film forming method in which a process of supplying and exhausting a precursor gas, a process of supplying and exhausting a reaction gas, and a process of generating plasma are sequentially repeated is used. In this film forming method, for example, when plasma is generated, it takes time to control electric power, pressure, gas concentration, and the like, and thus, it is difficult to improve a manufacturing throughput.